1. Field of the Invention
The present invention relates to a circuit for driving and controlling a second cache incorporated in a processor and comprising a plurality of RAM blocks. The invention relates to a second cache and a RAM, too. Further, the invention relates to a method of driving and controlling a second cache. More particularly, this invention relates to measures taken to save electric power in processing data at high speeds.
2. Description of the Related Art
In the past, processors had only an LBS (i.e., first cache). At present, processors having not only the first cache, but also the second cache, are used in increasing numbers. This is because the access to data should now be made at a higher speed than before. The storage capacity and access performance of the second cache have come to determine the operating efficiency of the processor. The storage capacity of the second cache has kept increasing. Importance has been placed only on methods of accessing the second cache fast and efficiently. The inevitably trend is that the power the processor consumes increases in proportion to the storage capacity of the RAM provided in the processor.
Recently, various attempts have been made to reduce the power consumption in processors. One of these attempts is to inhibit the supply of the clock signal to any RAM that need not be accessed, in accordance with whether a valid request has been made for the access to the second cache. The power consumption in the second cache can thereby be reduced.
FIG. 6 shows the configuration of a second cache. The second cache comprises 8 word blocks Word0 to Word7, each consisting of 16 RAMs. Each RAM consists of one of WAY0 to WAY3 and one of BANK0 to BANK3. The RAMs of each word block are controlled by a second-cache control unit 1.
In the prior art, the supply of the clock signal to all RAMs is inhibited as shown in FIG. 7, as long as the control unit 1 makes no valid requests for access to the second cache is made. When a valid request for the access to the second cache, any bank that needs the clock signal is determined from the address of the access request. Thus, the supply of the clock signal to any RAM that is not used is inhibited.
There are three types of access requests. They are ReaD request (RD MODE), WriTe request (WT_MODE), and MoDify request (MD_MODE). These requests are sent from the processor to the second cache through the second-cache control unit. In accordance with the mode pertaining to each access request, only a specific number of RAMs are the driven, as set forth below.
In RD_MODE, 32 RAMs (=4 ways×1 bank×8 words) are accessed.
In WT_MODE, 8 RAMs (=1 way×1 bank×8 words) are accessed.
In MD_MODE, 8 RAMs (=1 way×1 bank×8 words) are accessed.
FIG. 8 shows the clock-supply control circuit that is provided in the second cache. The bank value is defined by one of the addresses that access the second cache, i.e., ADRS<19:18>. The bank value for each RAM is determined from the bit content of the address ADRS. On the basis of the bank value and the type of access (i.e., RD_MODE in the case illustrated in FIG. 8), the RAM (i.e., way and bank) to which the clock signal should not be supplied (or should be supplied) is determined. A non-enable signal (or an enable signal) is supplied to the enable terminal of this RAM3. In the case depicted in FIG. 8, the RAMs for banks BANK1, 2 and 3 at ways WAY0 to WAY3 are stopped.
Known as a device related to the prior art described above is a semiconductor integrated circuit that enables the second cache, if necessary, to operate at an increased speed or at smaller power consumption. (See, for example, Japanese Patent Laid-Open No. 2003-242029.)
It is increasingly demanded that processors should operate faster. To meet the demand, the RAMs of the second cache are accessed in synchronism with the pipeline of any processor. This renders it difficult to inhibit the supply of the clock signal to the RAMs at an appropriate timing.
The conventional RAM is accessed once for every period 2τ of the request pipeline of the processor (τ is a unit time). Thus, the clock control signal needs to arrive within 2τ. For the pipelined RAM that can be accessed every τ, in synchronism with the request pipeline of the processor, the clock control signal must arrive at the time an access request comes.
To such a high-speed RAM, a request for input signals to the RAM can hardly be made at an appropriate time. This is why it is difficult to inhibit the supply of the clock signal to the RAMs at an appropriate timing.
The technique disclosed in Japanese Patent Laid-Open No. 2003-242029 is to suppress the data-processing speed for the purpose of reducing the power consumption. In this sense, the technique cannot achieve the object of the present invention, i.e., to reduce the power consumption, while maintaining the high data-processing speed.